Xiaomi's Three Chips: Trading Resources for Time, Betting on a Paradigm Shift in On-Device AI
Xiaomi unveiled three Xuanjie chips in one go, aggressively betting on memory interconnect, 3D stacking, and an all-AI architecture. It's trading resources for time, betting on a paradigm shift in on-device AI and vertical integration—but it still lags top-tier chip companies.
The argument · tap a timestamp to hear it
Chip capability is about system definition, not IP self-reliance
To judge whether a company can make chips, don't just count how many IP blocks it hand-crafts; look at how much system definition power it holds. Xiaomi's Xuanjie O1 uses ARM IP for CPU and GPU, but system integration and physical implementation are its own. Apple and Qualcomm excel at yearly iteration and continuous tape-outs—something latecomers lack. Xiaomi doesn't have a decade to learn slowly, so it's taking an aggressive route, advancing multiple high-risk technology lines simultaneously.
— Lao ShiO1's energy inefficiency stems from a missing shared water tank
The Xuanjie O1 lacks a system-level cache (SLC), causing power consumption to spike under heavy GPU load and hurting energy efficiency. An SLC is like a shared water tank in a neighborhood: the closer data is to compute units, the faster access and lower power. The O1 has many GPU cores but limited DDR bandwidth; many cores sit idle waiting for data, so utilization stays low—that's the bandwidth wall. The O3 adds a 16MB SLC, split into multiple cache blocks distributed across the chip, and designs an on-chip network scheduler to handle data consistency and access conflicts.
— Lao ShiARM's generic bus forced Xuanjie to build its own
ARM's off-the-shelf CHI+CMN solution is too generic, retaining compatibility and redundancy that hinder customization for Xuanjie. The O3 instead uses a self-developed X-Ring unified fabric, compatible with CHI but defining its own interconnect protocol, with custom high-speed routing hubs and memory controllers. This reduces protocol conversion overhead and lets data decide cache placement and paths based on need. Xiaomi claims protocol conversion overhead drops 75%, and static access latency is 82 nanoseconds—32% lower than the O1 and even lower than Apple's A19 Pro.
— Lao ShiCompute bottleneck shifts from matrix multiply to vector operations
The O3 adds AI units to every subsystem—CPU, GPU, ISP, etc.—so computation happens where data resides, reducing data movement. NPU cores drop from 6 to 4, but Tensor compute rises to 200 Tops because Xiaomi believes the bottleneck for large models is expanding from matrix multiplication to vector operations like Softmax, quantization, and KV cache. Vector units take up about the same area as Tensor units, with 6.8 times the multiply-accumulate units of the O1, and introduce a SMT-like architecture, similar to CUDA, to handle irregular parallel tasks.
— Lao ShiChips and models should be co-defined by the same company
Xiaomi partnered with MEMO to compress INT4 weights to 5 bits using a 5-value quantization method, with almost no loss in precision, cutting memory bandwidth and capacity needs by 30%. The 3-billion-parameter MEMO model runs on the O3, with prefill performance up 40% and decode up 45%. This ability to co-define chips and models is the closed-loop advantage of vertical integration—no waiting for others to define models before adapting.
— Lao Shi3nm performance is squeezed out standard cell by standard cell
The O3 uses the more mature N3P process, delivering 5% better performance at the same power and 5%-10% lower power at the same frequency. Xiaomi also made extensive process optimizations: self-developed standard cells grew from 480 in the O1 to over 2,400, covering various chip components; power delivery buffers' channels were compressed so power and signals route from module centers, boosting transistor density by 5%. The CPU shifted from 4 clusters to 3 clusters of 10 big cores, improving single-core performance by 31% and multi-core by 60%, surpassing the A19 Pro.
— Lao ShiNear-memory computing pushes phone memory bandwidth to 1.22TB/s
The Xuanjie O100 uses wafer-level 3D stacking: one compute wafer plus two memory wafers stacked vertically, connected via hybrid bonding, forming a near-memory computing architecture. It uses thousands of shorter, denser vertical interconnects for high bandwidth, with lower energy per bit shift—like an HBM for phones. Data: 28,762 data connections, 1.22TB/s bandwidth, far exceeding the tens of bits wide connections of traditional SoC-to-LPDDR. The compute layer has 14 independent cores, each with a RISC-V processor for control.
— Lao ShiCXMT's value lies in co-definition, not speed grades
Xiaomi partnered with CXMT to debut LPDDR6, reducing reliance on Samsung and SK Hynix. Even if CXMT offers the 10.667Gbps entry-level speed, Xiaomi can compensate for peak rate gaps with wider channels, larger SLC, and custom memory controllers. More importantly, the two co-validate and tune from the design stage, jointly defining a Chinese mobile memory subsystem solution. For CXMT, this proves its high-speed I/O and physical layer capabilities, earning a seat at the next-generation mobile memory table.
— Lao ShiXiaomi is betting not on chips but on a time window
First, it bets on a paradigm shift in on-device computing: AI's weight in SoCs keeps rising, phones become AI interaction gateways, and Xiaomi wants to be in the definer's seat. Second, it bets that vertical integration becomes a core competency for device companies—generic chips can't meet the fragmented needs of human, car, and home scenarios, so Xiaomi must own its compute architecture. Third, it bets on an uncertain time window, trading resources for time to compress the catch-up cycle, preferring to bear engineering risk rather than watch the window close.
— Lao ShiXuanjie is closing faster, but still hasn't cleared any of three hurdles
Top-tier SoC companies need three capabilities: self-developed CPU/GPU microarchitecture, self-developed 5G baseband, and continuous multi-generation tape-outs with tens of millions of shipments. Xuanjie currently meets none, still clearly behind the first tier—just closing faster. What truly reshapes the industry isn't a single dazzling chip but the sustained iteration capability a group of companies builds. Xuanjie's larger significance is proving Xiaomi's chip efforts haven't stopped and that it's moving forward with Chinese chip industry partners.
— Lao ShiIn their own words · checked verbatim
"To judge whether a company can really make chips, don't just stare at how many IP blocks it hand-crafts; you should look at how much system definition power it holds."
判断一家公司到底会不会造芯片，不要只盯着它自己手搓了多少个IP，更应该看它掌握了多少系统定义权。
Lao Shi3:02
"Xiaomi isn't slowly learning to make chips; it's trading resources for time, trying to build the complete capability stack of a mature chip company within a limited time window."
小米不是在慢慢学做芯片，而是在用资源换时间，在有限的时间窗口里，尽快搭出一家成熟芯片公司需要的完整能力站。
Lao Shi5:04
"As long as data is stored reasonably and distributed efficiently, the entire chip can benefit."
只要数据存的合理，颁得高效，整颗芯片都能因此而受益。
Lao Shi11:07
"Once it's done, you don't have to wait for someone else to define the model, then adapt a generic chip to it, and then figure out how to stuff it into a phone."
一旦做成，就不用等别人定义好的模型，再拿通用的芯片去适配，然后再考虑怎么塞到手机里。
Lao Shi15:11
"Better to bear more engineering and R&D uncertainty than to wait until the window truly closes and regret not having moved faster."
宁愿在多承担一些工程和研发上的不确定性，也不愿意等到窗口真的关上之后，再后悔当初没有快走几步。
Lao Shi25:18
Figures
| Xuanjie O3 protocol conversion overhead reduction | 75% | 11:07 |
| Xuanjie O3 static access latency | 82 nanoseconds | 11:07 |
| Xuanjie O3 dynamic access latency | 177 nanoseconds | 11:07 |
| Xuanjie O3 Tensor compute | 200 Tops | 13:10 |
| Xuanjie O3 vector compute improvement | 6.8x (3.13 TFLOP) | 14:10 |
| Xuanjie O3 single-core performance improvement | 31% | 17:11 |
| Xuanjie O3 multi-core performance improvement | 60% | 17:11 |
| Xuanjie O100 data connections | 28,762 | 20:13 |
Glossary
- SLC / System-Level Cache
- A cache shared by multiple compute units on a chip, like a shared water tank in a neighborhood.
- Hybrid Bonding
- A wafer-level 3D stacking interconnect technology using direct copper-to-copper connections, offering high bandwidth and low power.
- Near-Memory Computing
- Placing memory and compute units close together to reduce data movement distance, improving bandwidth and energy efficiency.
- Bandwidth Wall
- A performance bottleneck where data movement capability limits performance, so adding more compute cores doesn't help.
- SMT / Simultaneous Multithreading
- A parallel processing architecture that can manage multiple task groups simultaneously, improving compute unit utilization.
How to listen
Investors focused on Xiaomi's chip efforts, chip industry engineers, product managers, and tech professionals wanting to understand on-device AI trends.
The first three minutes, discussing the definition of self-development, can be skipped—jump straight to the technical analysis.