Xiaomi's Three Chips at Once: Trading Resources for Time, Betting on a Paradigm Shift in On-Device AI
Xiaomi released three Xuanjie chips in one go, aggressively betting on memory interconnect, 3D stacking and an all-AI architecture, trading resources for time, wagering on a paradigm shift in on-device AI and vertical integration capabilities, but still with a clear gap to top-tier chip companies.
The argument · tap a timestamp to hear it
Whether a company can make chips depends on system definition power, not IP self-development rate
Judging whether a company can make chips cannot just look at how many IPs it hand-crafted, but at how much system definition power it holds. Although Xiaomi's Xuanjie O1 uses ARM IP for CPU and GPU, system integration and physical implementation are all done in-house. Apple and Qualcomm are strong because they can iterate annually and tape out continuously, which is what latecomers lack most. Xiaomi doesn't have ten years to learn slowly, so it chose an aggressive route, advancing multiple high-risk technology lines simultaneously.
— Lao ShiThe culprit for O1's poor energy efficiency is the lack of a shared water tank
Xuanjie O1 lacks a system-level cache (SLC), causing GPU power consumption to be uncontrollable under high load and energy efficiency to be unsatisfactory. SLC is like a shared large water tank in a community; the closer data is to the compute unit, the faster the access and the lower the power consumption. O1's GPU has many cores but limited DDR bandwidth, so many cores are waiting for data, and utilization cannot go up—this is the bandwidth wall. O3 adds 16MB SLC, split into multiple cache blocks distributed across the chip, and designs an on-chip network scheduling system to solve data consistency and access conflicts.
— Lao ShiARM's public bus is too generic; Xuanjie had to build its own
ARM's public CHI+CMN solution is too generic, requiring compatibility and redundancy designs, making it hard to customize for Xuanjie. O3 simply developed its own X-Ring unified fusion bus, compatible with CHI but defining its own interconnect protocol, and self-developed high-speed road network scheduling center and memory controller. This reduces protocol conversions, and data can decide cache location and path based on demand. Xiaomi data claims protocol conversion overhead reduced by 75%, static access latency 82 nanoseconds, 32% lower than O1, even lower than Apple A19 Pro.
— Lao ShiThe compute bottleneck is shifting from matrix multiplication to vector operations
O3 adds AI units to each subsystem like CPU, GPU, ISP, letting computation happen where the data is, reducing data movement. NPU core count reduced from 6 to 4, but Tensor compute power increased to 200Tops, because Xiaomi judges that the large model bottleneck is expanding from matrix multiplication to vector operations, such as Softmax, quantization, KVCache, etc. The vector unit area is about the same as Tensor, with 6.8 times the number of multiply-accumulate units as O1, and introduces an SMT-like architecture, similar to CUDA, handling irregular parallel tasks.
— Lao ShiChips and models should be defined together by the same company
Xiaomi collaborates with MEMO, using a 5-value quantization method to compress INT4 weights to 5 bits, with almost no precision loss, reducing memory bandwidth and capacity requirements by 30%. The 3-billion-parameter MEMO model deployed on O3 improves prefill performance by 40% and decode by 45%. This ability to jointly define chips and models is a closed-loop advantage of vertical integration, without waiting for others to define models before adapting.
— Lao Shi3nm performance is squeezed out bit by bit from standard cells
O3 uses the more mature N3P process, improving performance by 5% at the same power, and reducing power by 5%-10% at the same frequency. Xiaomi also did a lot of process optimization: self-developed standard cells increased from 480 in O1 to over 2400, covering all chip units; compressing the power supply buffer channel, allowing power and signals to go through the middle of the module, increasing transistor density by 5%. CPU changed from 4 clusters to 3 clusters of 10 all-big cores, single-core performance improved by 31%, multi-core by 60%, surpassing A19 Pro.
— Lao ShiNear-memory computing pushes phone memory bandwidth to 1.22TB/s
Xuanjie O100 uses wafer-level 3D stacking, with one compute wafer and two memory wafers vertically stacked, interconnected via Hybrid Bonding, forming a near-memory computing architecture. It uses thousands of shorter and denser vertical connections to achieve high bandwidth, with lower energy per bit shift, similar to mobile HBM. Data: 28762 data connections, bandwidth 1.22TB/s, far exceeding traditional SoC and LPDDR connections with dozens of bits width. The compute layer has 14 independent cores, each with a RISC-V processor for control.
— Lao ShiChangXin's value is not in speed grades, but in joint definition
Xiaomi partners with ChangXin to debut LPDDR6, reducing dependence on Samsung and SK Hynix. Even if ChangXin provides a starting grade of 10.667Gbps, Xiaomi can compensate for peak speed gaps through wider channels, larger SLC, and self-developed memory controllers. More importantly, the two sides jointly verify and tune from the design stage, jointly defining China's mobile memory subsystem solution. For ChangXin, it proves its high-speed IO and physical layer capabilities, sitting at the table for the new generation of mobile memory.
— Lao ShiXiaomi is not betting on chips, but on a time window
First, betting on a paradigm shift in on-device computing, with AI weighing more and more in SoCs, phones becoming AI interaction entry points, and Xiaomi wanting to be in the definer's position. Second, betting that vertical integration becomes the core competitiveness of terminal companies, as general-purpose chips cannot meet the fragmented needs of all scenarios of people, cars, and homes, and must master their own computing architecture. Third, betting on an uncertain time window, trading resources for time, compressing the technology catch-up cycle, preferring to bear engineering risks rather than wait for the window to close.
— Lao ShiXuanjie catches up faster, but none of the three thresholds are passed
Top SoC companies need three capabilities: self-developed CPU/GPU microarchitecture, self-developed 5G baseband, and continuous stable tape-outs across multiple generations with tens of millions of shipments. Xuanjie currently satisfies none, still with a clear gap to the first tier, just catching up faster. What truly changes the industry landscape is not a single stunning chip, but a group of companies building continuous iteration capabilities. Xuanjie's greater significance is proving Xiaomi's chip efforts haven't stopped, and starting to move forward with Chinese chip industry partners.
— Lao ShiIn their own words · checked verbatim
Judging whether a company can really make chips, don't just stare at how many IPs it hand-crafted, but look more at how much system definition power it holds.
判断一家公司到底会不会造芯片，不要只盯着它自己手搓了多少个IP，更应该看它掌握了多少系统定义权。
Lao Shi3:02
Xiaomi is not slowly learning to make chips, but trading resources for time, in a limited time window, building up the complete capability station a mature chip company needs as quickly as possible.
小米不是在慢慢学做芯片，而是在用资源换时间，在有限的时间窗口里，尽快搭出一家成熟芯片公司需要的完整能力站。
Lao Shi5:04
As long as data is stored reasonably and issued efficiently, the entire chip can benefit from it.
只要数据存的合理，颁得高效，整颗芯片都能因此而受益。
Lao Shi11:07
Once done, there's no need to wait for others to define a model, then use general-purpose chips to adapt, and then consider how to stuff it into a phone.
一旦做成，就不用等别人定义好的模型，再拿通用的芯片去适配，然后再考虑怎么塞到手机里。
Lao Shi15:11
I'd rather bear more engineering and R&D uncertainty than wait until the window really closes and then regret not having walked a few steps faster.
宁愿在多承担一些工程和研发上的不确定性，也不愿意等到窗口真的关上之后，再后悔当初没有快走几步。
Lao Shi25:18
Figures
| Xuanjie O3 protocol conversion overhead reduction | 75% | 11:07 |
| Xuanjie O3 static access latency | 82 nanoseconds | 11:07 |
| Xuanjie O3 dynamic access latency | 177 nanoseconds | 11:07 |
| Xuanjie O3 Tensor compute power | 200Tops | 13:10 |
| Xuanjie O3 vector compute power improvement | 6.8 times (3.13 TFLOP) | 14:10 |
| Xuanjie O3 single-core performance improvement | 31% | 17:11 |
| Xuanjie O3 multi-core performance improvement | 60% | 17:11 |
| Xuanjie O100 data connections | 28762 | 20:13 |
Glossary
- SLC / System-Level Cache
- A cache shared by multiple compute units within a chip, like a shared large water tank in a community.
- Hybrid Bonding
- A wafer-level 3D stacking interconnect technology that connects directly through copper pillars, offering high bandwidth and low power consumption.
- Near-Memory Computing
- Placing storage and compute units close together to reduce data movement distance, improving bandwidth and energy efficiency.
- Bandwidth Wall
- Data movement capability becomes the performance bottleneck, and no matter how many compute cores there are, they cannot be fully utilized.
- SMT / Simultaneous Multithreading
- A parallel processing architecture that can manage multiple sets of tasks simultaneously, improving compute unit utilization.
How to listen
Investors watching Xiaomi's chip efforts, chip industry engineers, product managers, and tech professionals wanting to understand on-device AI trends.
The first 3 minutes on the definition of self-development can be skipped; go straight to the technical analysis.