Three Xiaomi Chips at Once: Trading Resources for Time, Betting on an On-Device AI Paradigm Shift
Xiaomi shipped three Xuanjie (玄界) chips in one go, an aggressive bet on memory interconnect, 3D stacking and an all-AI architecture — spending resources to buy time, wagering on a shift in the on-device AI paradigm and on vertical integration, while still falling clearly short of the top-tier chip companies.
The argument · tap a timestamp to hear it
Chipmaking ability is measured by system definition power, not in-house IP
Whether a company can really build chips is not settled by counting how many IP blocks it hand-rolled; it is settled by how much system definition power it holds. Xiaomi's Xuanjie O1 uses ARM IP for its CPU and GPU, but system integration and physical implementation were done in-house. What Apple and Qualcomm are strong at is iterating year after year and taping out continuously, and that is exactly what a latecomer lacks most. Xiaomi does not have ten years to learn slowly, so it chose the aggressive route: pushing several high-risk technology tracks forward at the same time.
— Lao ShiO1's poor efficiency traces back to one missing shared water tank
Xuanjie O1 has no system level cache (SLC), so under heavy GPU load power draw cannot be contained and efficiency suffers. An SLC is like the shared water tank serving a residential compound: the closer the data sits to the compute units, the faster the access and the lower the power. O1 has plenty of GPU cores but limited DDR bandwidth, so many of those cores sit waiting for data and utilisation never climbs — that is the bandwidth wall. O3 fills the gap with 16MB of SLC, split into multiple cache blocks distributed across the die, plus an on-chip network scheduling system to handle data coherence and access contention.
— Lao ShiARM's off-the-shelf bus is too generic, so Xuanjie built its own
ARM's stock CHI plus CMN scheme is too general-purpose: it has to preserve compatibility and redundancy, which makes it hard to tailor for Xuanjie. So O3 simply built its own — X-Ring, a unified fused bus that stays CHI-compatible while defining its own interconnect protocol, along with an in-house high-speed network scheduling hub and memory controller. That means fewer protocol conversions, and data can be placed and routed according to what it actually needs. Xiaomi's own figures: protocol conversion overhead down 75%, static access latency of 82 nanoseconds, 32% lower than O1 and even below Apple's A19 Pro.
— Lao ShiThe compute bottleneck is shifting from matrix multiplication toward vector operations
O3 adds an AI unit to every subsystem — CPU, GPU, ISP — so that computation happens where the data already sits and less data has to be moved around. NPU core count drops from 6 to 4, yet Tensor compute rises to 200Tops, because Xiaomi's read is that the large-model bottleneck is spreading from matrix multiplication into vector operations such as Softmax, quantisation and KVCache. The vector units take up roughly as much area as the Tensor ones, the multiply-accumulate count is 6.8 times that of O1, and an SMT-like architecture, similar to CUDA, handles irregular parallel workloads.
— Lao ShiChip and model should be defined together, by the same company
Xiaomi worked with MEMO on a 5-value quantisation method that compresses INT4 weights down to 5 bits with almost no loss of accuracy, cutting memory bandwidth and capacity requirements by 30%. MEMO's 3-billion-parameter model deployed on O3 gains 40% in prefill performance and 45% in decode. This ability to define chip and model jointly is the closed-loop advantage of vertical integration: no waiting for someone else to finish defining a model before you adapt to it.
— Lao Shi3nm performance gets squeezed out one standard cell at a time
O3 uses the more mature N3P process: 5% more performance at the same power, 5%-10% less power at the same clock. Xiaomi layered a great deal of process optimisation on top of that. In-house standard cells went from 480 on O1 to more than 2,400, covering every block on the chip; compressing the power-delivery buffer channel lets power and signal run through the middle of a module, lifting transistor density by 5%. The CPU moves from 4 clusters to 3, ten cores all big cores, with single-core performance up 31% and multi-core up 60%, ahead of the A19 Pro.
— Lao ShiNear-memory computing pushes phone memory bandwidth to 1.22TB/s
Xuanjie O100 uses wafer-level 3D stacking: one compute wafer and two memory wafers stacked vertically and joined by Hybrid Bonding, forming a near-memory computing architecture. It gets its bandwidth from many thousands of shorter, denser vertical links, at lower energy per bit moved — in effect HBM for a phone. The numbers: 28762 data connections and 1.22TB/s of bandwidth, far beyond the few-dozen-bit-wide links between a conventional SoC and LPDDR. The compute layer holds 14 independent cores, each paired with a RISC-V processor for control.
— Lao ShiCXMT's value is not the speed grade, it is joint definition
Xiaomi partnered with CXMT (长鑫) to launch LPDDR6 first, reducing its dependence on Samsung and SK Hynix. Even if what CXMT supplies starts at the 10.667Gbps grade, Xiaomi can make up the peak-rate gap with wider channels, a larger SLC and its own memory controller. The more important part is that the two sides jointly validated and tuned from the design stage onward, co-defining a Chinese mobile memory subsystem. For CXMT, it proves its high-speed IO and physical-layer capability and wins it a seat at the next-generation mobile memory table.
— Lao ShiXiaomi is betting on a time window, not on a chip
First, it is betting on a shift in the on-device computing paradigm: AI carries ever more weight inside the SoC, the phone becomes the entry point for AI interaction, and Xiaomi wants to stand where the definitions are made. Second, it is betting that vertical integration becomes the core competitive advantage of a device company — general-purpose silicon struggles to serve the fragmented demands of the human-car-home footprint, so you have to own your own compute architecture. Third, it is betting on an uncertain time window, trading resources for time to compress the catch-up cycle, willing to carry engineering risk rather than wait for that window to close.
— Lao ShiXuanjie is closing the gap faster, but clears none of the three bars
A top-tier SoC company needs three capabilities: its own CPU and GPU microarchitecture, its own 5G baseband, and consecutive generations of stable tape-outs shipping in the tens of millions. Xuanjie satisfies none of them today; the gap to the first tier remains clear, and all that has changed is the speed of the chase. What reshapes an industry is not one dazzling chip but a group of companies building the ability to iterate continuously. Xuanjie's larger significance is that it proves Xiaomi's chip effort has not stopped, and that it has begun moving forward together with partners across China's chip industry.
— Lao ShiIn their own words · checked verbatim
To judge whether a company can really build chips, do not just fixate on how many IP blocks it hand-rolled itself; look instead at how much system definition power it holds.
判断一家公司到底会不会造芯片，不要只盯着它自己手搓了多少个IP，更应该看它掌握了多少系统定义权。
Lao Shi3:02
Xiaomi is not slowly learning how to make chips. It is trading resources for time, racing to assemble, inside a limited window, the full stack of capabilities a mature chip company needs.
小米不是在慢慢学做芯片，而是在用资源换时间，在有限的时间窗口里，尽快搭出一家成熟芯片公司需要的完整能力站。
Lao Shi5:04
As long as the data is stored sensibly and moved efficiently, the entire chip benefits from it.
只要数据存的合理，颁得高效，整颗芯片都能因此而受益。
Lao Shi11:07
Once this works, you no longer have to wait for someone else to define a model, then take a general-purpose chip and adapt it, and only then work out how to cram it into a phone.
一旦做成，就不用等别人定义好的模型，再拿通用的芯片去适配，然后再考虑怎么塞到手机里。
Lao Shi15:11
Better to shoulder some extra engineering and R&D uncertainty than to wait until the window has actually closed and then regret not having moved a few steps faster.
宁愿在多承担一些工程和研发上的不确定性，也不愿意等到窗口真的关上之后，再后悔当初没有快走几步。
Lao Shi25:18
Figures
| Xuanjie O3 protocol conversion overhead reduction | 75% | 11:07 |
| Xuanjie O3 static access latency | 82 nanoseconds | 11:07 |
| Xuanjie O3 dynamic access latency | 177 nanoseconds | 11:07 |
| Xuanjie O3 Tensor compute | 200Tops | 13:10 |
| Xuanjie O3 vector compute increase | 6.8x (3.13 TFLOP) | 14:10 |
| Xuanjie O3 single-core performance gain | 31% | 17:11 |
| Xuanjie O3 multi-core performance gain | 60% | 17:11 |
| Xuanjie O100 data connections | 28762 lanes | 20:13 |
Glossary
- SLC / System Level Cache
- A cache shared by multiple compute units on a chip, like the big shared water tank serving a residential compound.
- Hybrid Bonding
- A wafer-level 3D stacking interconnect technology using direct copper-pillar connections, giving high bandwidth at low power.
- Near-memory computing
- Placing memory and compute units close together to shorten data movement, raising bandwidth and energy efficiency.
- Bandwidth wall
- When data movement capacity becomes the performance bottleneck, so adding more compute cores no longer helps.
- SMT / Simultaneous Multi-Threading
- A parallel processing architecture that manages several groups of tasks at once, raising compute unit utilisation.
How to listen
Investors following Xiaomi's silicon effort, chip industry engineers, product managers, and anyone in tech trying to understand where on-device AI is heading.
The first 3 minutes on what counts as in-house design can be skipped — go straight to the technical analysis.