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TechTechPotato

Ian Cutress on chips and data centers, often with first-hand vendor interviews

Deep reads here8 / 15 episodes
Cadence~1 every 2.1 days
Latest2026-09-03
TopicsAI & Tech
PriorityT2
11:47
TechTechPotato 0902

The superconducting-chip claim: change the temperature range, not the process node

Move the logic into the liquid-helium range and replace transistors with superconducting switches — that is Snowcap's bet: tape out RISC-V first, then claim that 28nm-class logic can deliver 5nm-class performance.

8 Points 7 Quotes Superconducting computingChip architecture
11:10
TechTechPotato 0831

AI Chip Shipments Are About to Jump an Order of Magnitude: From One Million Units to 15 Million

Broadcom's president walks through an AI chip roadmap that runs from a million units toward 15 million. The ‘beast’ is the largest package: eight stackable compute dies plus 16 HBM. Four of the five leading frontier labs are working with them.

8 Points 7 Quotes Custom siliconASIC
31:10
TechTechPotato 0825

OpenAI's Own Chip Is 100x Ahead? That's a Self-Chosen Benchmark on a Dedicated Stack

OpenAI's first in-house chip, Jalapeno, beats the GB200 by 100x on a benchmark OpenAI picked — but that result comes from a dedicated chip running dedicated models on a dedicated software stack; the real moat is system integration and pricing power.

8 Points 6 Quotes Chip designOpenAI
21:44
TechTechPotato 0825

Intel Drops EMIB for UCIe: 1.2GB of Cache Behind 256 Cores

Diamond Rapids is expected in 2027 with up to 256 P-cores, 1.2GB of last-level cache and 16 channels of DDR5; it replaces EMIB with trimmable compute building blocks and a UCIe interconnect, and the huge cache is its answer to the AI era.

8 Points 6 Quotes CPU architectureData centers
TechTechPotato 0823

What Etched's chip really solves may be bandwidth, not compute

Etched welds the transformer into hardware with 0.45-volt ultra-low-voltage transistors and direct cross-chip SRAM access, but the host suspects the problem actually being solved is bandwidth, not compute.

8 Points 8 Quotes AI chipsTransformer-specific chips
23:20
TechTechPotato 0819

Cerebras hits 4400 tok/s on a single chip: inference speed is the moat

Cerebras pushes WSE 3.5 to 4400 tok/s per chip, and the CS4 rack packs three wafers into a 120kW cabinet. The core argument: inference has to be split into prefill and decode, and speed is the moat.

8 Points 7 Quotes Inference chipsCerebras
30:20
TechTechPotato 0810

Custom Silicon Isn't About Saving Money, It's About Escaping Nvidia's Generational Grip

The real motive behind hyperscaler custom silicon is not cost but control: not being held hostage to Nvidia's generational cadence, while using sheer scale to squeeze down networking and compute costs. The Broadcom tax is cheaper than the Nvidia tax, but only the largest players can afford to play.

8 Points 7 Quotes HyperscalersCustom silicon
16:08
TechTechPotato 0806

AMD Buys Talus: Burning AI Models Into Silicon, 17,000 Tokens a Second

AMD has acquired Talus, a startup that builds custom chips for one specific AI model each and reaches 17,000 tokens per second. It marks a turn in AI inference toward non-programmable, model-specific silicon.

6 Points 5 Quotes AI chipsAMD