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TechTechPotato

Ian Cutress on chips and data centers, often with first-hand vendor interviews

Deep reads here8 / 15 episodes
Cadence~1 every 2.0 days
Latest2026-10-16
TopicsAI & Tech
PriorityT2
11:47
TechTechPotato 0902

Superconducting chip claim: don't change the process node, change the temperature zone — 28nm logic can hit 5nm performance

Move logic into the liquid helium temperature zone and replace transistors with superconducting switches. That's Snowcap's bet: tape out RISC-V first, then claim 28nm-class logic can deliver 5nm-class performance.

8 Points 7 Quotes Superconducting computingChip architecture
11:10
TechTechPotato 0831

AI chip shipments are about to jump an order of magnitude: from a million units to 15 million

Broadcom's president lays out the AI chip roadmap: from a million units to 15 million, with the "beast" being the largest package at 8 stackable compute dies plus 16 HBM, and four of the five frontier labs working with the company.

8 Points 7 Quotes Custom siliconASIC
31:10
TechTechPotato 0825

OpenAI's Own Chip Is 100x Ahead? That's a Self-Chosen Benchmark on a Dedicated Stack

OpenAI's first in-house chip, Jalapeno, beats the GB200 by 100x on a benchmark OpenAI picked — but that result comes from a dedicated chip running dedicated models on a dedicated software stack; the real moat is system integration and pricing power.

8 Points 6 Quotes Chip designOpenAI
21:44
TechTechPotato 0825

Intel Drops EMIB for UCIe: 1.2GB of Cache Behind 256 Cores

Diamond Rapids is expected in 2027 with up to 256 P-cores, 1.2GB of last-level cache and 16 channels of DDR5; it replaces EMIB with trimmable compute building blocks and a UCIe interconnect, and the huge cache is its answer to the AI era.

8 Points 6 Quotes CPU architectureData centers
TechTechPotato 0823

What Etched's chip really solves may be bandwidth, not compute

Etched welds the transformer into hardware with 0.45-volt ultra-low-voltage transistors and direct cross-chip SRAM access, but the host suspects the problem actually being solved is bandwidth, not compute.

8 Points 8 Quotes AI chipsTransformer-specific chips
23:20
TechTechPotato 0819

Cerebras hits 4400 tok/s on a single chip: inference speed is the moat

Cerebras pushes WSE 3.5 to 4400 tok/s per chip, and the CS4 rack packs three wafers into a 120kW cabinet. The core argument: inference has to be split into prefill and decode, and speed is the moat.

8 Points 7 Quotes Inference chipsCerebras
30:20
TechTechPotato 0810

In-House Silicon Isn't About Saving Money, It's About Escaping Nvidia's Generational Lock-In

The real motive behind hyperscaler in-house chips isn't cost savings but control: avoiding being held hostage to Nvidia's generational cadence, while using scale to compress networking and compute costs. The Broadcom tax is cheaper than the Nvidia tax, but only the biggest players can afford to play.

8 Points 7 Quotes HyperscalersIn-House Silicon
16:08
TechTechPotato 0806

AMD buys Talus: burning AI models into silicon, 17,000 tokens per second

AMD has acquired Talus, a startup that builds chips customised for specific AI models and hits 17,000 tokens per second. It marks AI inference moving toward non-programmable, model-specific silicon.

6 Points 5 Quotes AI chipsAMD