TSMC Trucks Half-Finished Wafers Between Fabs: The Secret Weapon of AI Capacity
TSMC exploits the more than 90% tool overlap between N5 and N7 to truck half-processed wafers from its Tainan fab to Taichung for finishing, freeing up AI capacity while N5 converts to N3. The foundation of the AI boom is a fleet of ordinary trucks.
The argument · tap a timestamp to hear it
The money spent this year only becomes capacity two years later
TSMC is building new fabs in three places in Taiwan at once: Fab 20 in Baoshan, Hsinchu; Fab 22 in Nanzi, Kaohsiung; and Fab 25 in Taitung, which so far is only land. There is also AP7, an advanced packaging fab in Chiayi. More than $60 billion in capital expenditure has already been allocated for 2026. Yet C.C. Wei and other executives concede that the money spent in 2026 will not reach the market until 2028. AI demand still cannot be met, and Nvidia wants chips now. TSMC holds one more card: cross-node utilization.
Node names mean nothing; the real node is a set of tools
The most open secret in semiconductor manufacturing is that logic node names mean nothing. TSMC's node roadmap is not a straight line from N3 to N2 to A14; it splits like ASCII art. N3 branches into N3E, N3P, N3X and N3C; N2 branches into N2P, N2X and A16. Once a node enters the fab, the manufacturing team keeps experimenting and yields climb point by point into the mid-80s. When enough improvements accumulate, they get repackaged as a new node -- N6 was born out of N7 -- or the improvements are saved for a future node. In the end, a node is a collection of tools and recipes.
The end of depreciation is not pure profit; old fabs get stranded
One of a fab's biggest costs is depreciation, a non-cash charge that stands for the useful life of the tools. After five to seven years the fab is fully depreciated, and in theory everything left after operating costs is profit. In reality tools always break, which is why Charlie Munger called EBITDA "BS earnings". When a large customer moves up a node, the old fab is left with an enormous hole in its capacity: Apple moved from N7 to N5, and the Taichung fab had to go find another customer. N2 is too new and too strange, N3 is the sweet spot, N4 is mature and still leading, while N7 and N6 are stuck in the middle -- too far from the frontier, and expensive next to 28nm. Once utilization drops below 70%, a fab starts losing money.
Above the transistor, the layers can be identical across nodes
A semiconductor is stacked in layers: transistors at the bottom, and above them the copper or aluminum metal interconnect layers, the BEOL. The finest lines are in the lowest metal layers -- N5's M1 has a pitch of roughly 28-30 nanometers -- and the higher you go the wider they get, up to 1.5 or even 3 microns at the top. That structure is shared across nodes, so many process steps are the same or similar between N16, N10, N7, N6, N5, N4 and N3. The critical transistor layers do differ, but the layers above the transistor can be completely identical. This is also why old DUV machines are still in heavy use. For the past decade, TSMC has used this layer overlap to keep its fabs from being stranded.
N10, N7 and N5 are really one single pool of capacity
In 2015, co-CEO Mark Liu said on an earnings call that 20nm and 16nm had 95% tool overlap, so a customer that wanted to upgrade could have its 20nm capacity converted to 16nm. In 2018, C.C. Wei said N10, N7 and N7+ had 90% overlap -- N7+ being the custom version with EUV added, built for Huawei. CFO Laura Ho added that the overlap from N7 to N5 was also more than 90%. That means N10, N7 and N5 can be treated as one enormous pool of capacity, and old fabs need not sit idle when customers move up. Conversion is not free, but it saves billions of dollars of capital expenditure.
The claim that N7 could not convert to N3 expired within a year
The AI era needs a great deal of N3 capacity. N5 and N3 have 90% tool overlap and both sit in Fab 18 in Tainan, connected by a giant wafer bridge, so conversion is easy. In 2024 TSMC began converting N5 to N3, at the cost of a bite out of gross margin. On the Q1 2024 earnings call, C.C. Wei was asked whether N7 could be converted to N3 in the same way. He said it was much harder, because N5 and N3 are in the same fab while N7 is in Taichung, about 100 miles away; he also said N7 demand would come back. By early 2025 he had changed his answer: for future AI products (that is, Vera Rubin) converting N5 was necessary, but N5 demand was strong as well, so the timing had to be chosen carefully -- and they had already worked out a way for N7 capacity to support N5.
The foundation of the AI ecosystem is a fleet of low-tech trucks
Once TSMC's wafers leave the front-end fabs, they have to travel to the advanced packaging fabs in Chiayi or Miaoli for CoWoS and InFO. How do you move wafers worth $20,000 each? In semi-custom modified trucks, carrying a few dozen FOUPs, running on Taiwan's highways like any ordinary freight vehicle. TSMC's ESG site even discusses improving working conditions for the truck drivers. Now TSMC is scaling that trucking service up massively: the Tainan fab processes only the critical N3 or N5 layers, then the unfinished wafers are loaded onto trucks and driven 100 miles to Taichung, where the underutilized N7/N6 fab finishes them. That lets Tainan put everything into the critical work. The largest infrastructure on earth, the foundation of the AI ecosystem, rests on a fleet of low-tech trucks.
In their own words · checked verbatim
One of the worst kept secrets in semiconductor manufacturing is that logic process node names mean nothing.
It's not a smooth N3 to N2 to A14 transition.
After a few years, maybe five to seven, the fab becomes fully depreciated and their revenue, net of operating costs, becomes all profit, in theory.
The point being that TSMC can avoid fab strandings by managing N10, N7, and N5 as a single massive pool of capacity.
the world's largest infrastructure build-out, the foundation of the AI ecosystem is dependent on a fleet of low-tech trucks hoofing it on Taiwan's highways.
Figures
| 2026 capital expenditure | More than $60 billion | 0:05 |
| N7 fab utilization (early 2023) | Dropped below 70% | 7:10 |
| N5 M1 metal layer pitch | 28-30 nanometers | 7:10 |
| 20nm to 16nm tool overlap | 95% | 9:15 |
| N10/N7/N7+ tool overlap | 90% | 9:15 |
| N7 to N5 tool overlap | More than 90% | 9:15 |
| Straight-line distance from the N5 fab to the N7 fab | About 100 miles | 11:15 |
Glossary
- cross-node utilization
- Treating the capacity of several logic nodes as one unified pool, meeting new demand by converting old fabs and shipping wafers between them.
- gate-all-around (GAA)
- A new transistor structure in which the gate wraps around the channel on all sides, adopted at nodes such as N2.
- back end of the line (BEOL)
- The stage that builds the metal interconnect layers above the transistors, used to carry signal and power.
- CoWoS
- TSMC's 2.5D advanced packaging, which places multiple dies on a silicon interposer and interconnects them.
- FOUP
- The standard wafer carrier, protecting wafers inside the fab and in transit. The transcript renders it as FOOP.
How to listen
Investors and semiconductor professionals watching TSMC capacity and the AI chip supply chain; engineers who want to understand why node numbers do not describe the actual process.
No section has to be skipped; listeners unfamiliar with process detail can skip the metal-layer explanation at 7:10-8:13.