AI Chip Design Is Real, but Verification Remains the Top Bottleneck
AI can already write RTL autonomously, but the real bottleneck in the chip pipeline is verification: it eats up more than half of development time, and AI still can't answer 'what to test.' OpenAI's twenty-person team can shorten the front end, but the back end still has to be left to humans.
The argument · tap a timestamp to hear it
K3 has only a front end, no back end
The raw material for the 'AI 48-hour tapeout' is a small inference accelerator called Nano KPU that Kimi unveiled: 238,000 parameters, about 1.46 million standard cells, 0.277MB SRAM, claiming to close timing at 100 MHz within 4 square millimeters and decode at 8,700 tokens/s. But the host looked closely: this RTL went through functional verification only — no cell placement, routing, physical verification, or sign-off. The so-called 'timing closure' relies on estimates, and 100 MHz is not impressive even in an open-source 45nm library; human designers using the same library can reach 20-450 MHz, and commercial processes can go to 1-3 GHz. K3's goal is not to make a good chip but to prove that an agent can autonomously reach functional completeness.
AI writing RTL is nothing new
Many people think AI writing chips started with K3, but as early as 2020, NYU researchers used GPT-2 to generate beginner-level RTL, reporting 94.8% accuracy. The now-defunct eFabless ran AI design contests, and Will Salcedo's GPT-4-generated design actually went to tapeout — one of the earliest known LLM-designed tapeouts, according to the host. 'AI writing RTL' itself is not the innovation; what has changed is that an agent can run unattended from scratch to functional completeness — the autonomy of the process has been refined.
The agent's future lies in wrapping toolchains
While fully autonomous design is still out of reach, the real product form is wrapping LLMs around EDA toolchains: the LLM directs deterministic EDA tools via interfaces like MCP or APIs, much like Claude Code lets models call computer tools. Synopsys, Cadence, and Siemens all have long-term goals of opening up their stacks, handing data feedback and control to agents that can run for hours or overnight. Siemens demonstrated at Semicon Taiwan: an agent dropped hundreds of standard cells one by one into a simulator, measuring load, speed, and power for later design lookup. Re-doing this tedious work for each new process node is exactly the kind of thing you hand to AI before you leave work.
Even the best results keep a human in the loop
Former xAI engineer Christina Lee's post is the most convincing breakdown the host has seen. Her meta-harness has two layers: the inner layer lets the model call EDA tools to write RTL, synthesize, place and route, and verify; the outer layer lets the model review what went right and wrong in the previous round, propose improvements, and run again. The first phase only did a MAC multiply-accumulate array, iterating from 900 MHz to 1 GHz over multiple rounds; the second phase connected the MAC to SRAM and other modules, and complexity immediately rose. Note that a human has been holding the wheel all along: the so-called 'goal strings' are likely provided by the outer model as a reference, but the selection and final sign-off rest with the human. AI is not the boss; it's the co-pilot.
What's truly scary about Jalapeno is the 20-person team
OpenAI's Jalapeno demo made many people focus on 'RTL to tapeout in just 9 months.' The host reminds us: Synopsys has said elsewhere, in an unrelated context, that using their tools without AI also takes about 9 to 12 months; the chip itself is not complex, and the starting point is unclear — the architecture concept only began in October 2024. What really stands out is the team size: only 20 to 30 people stood up at the end of the talk. And this group's token consumption consistently ranks near the top of OpenAI's internal leaderboards, with RTL still being changed the day before the freeze. If such a small team can do it, the number of people needed for chip jobs in the future could drop by an order of magnitude — perhaps that's why they don't emphasize it in the slides.
Verification is the real bottleneck in AI chip design
The whole industry talks up the front-end RTL but glosses over the back end: OpenAI's presentation slides spend a lot on spec and RTL, but the back end, the host guesses, is handled by partner Broadcom, thanked only on slide 34; Lee also hands the back end to Yosys/OpenLane. The mechanistic asymmetry is that PPA (power/performance/area) optimization is a closed loop — generate, verify, measure PPA — and AI has a clear reward signal. Verification is not: passing or failing a test doesn't tell AI how far it is from full coverage, and 'what to test' still has to come from humans. Chip bugs can't be changed once taped out, so seeing a defect on the first look at TSMC's silicon is the most crushing moment. This explains why verification can consume 50 to 70% of development time, and echoes Shibo Chen's remark that 'AI designs, humans verify' is the only reassuring combination.
The biggest threat to front-end wrappers is OpenAI itself
Silicon Valley is spawning a wave of startups that wrap frontier models with proprietary knowledge to write RTL. The risk the host sees: Anthropic and OpenAI both own the models and are building chips themselves; if they decide to open up their chip-specific models, the differentiation of front-end wrappers disappears. So he prefers to bet on teams that move toward the back end and verification, where end-to-end moats exist. How fast is this field moving? While he was writing, Architect Labs announced that its Redwood chip was fully produced and verified by AI, with specs written only by two architects; even TSMC's 3D IC talk used 'agentic AI.' The host worries that his judgment could be overturned by new news within a week or two.
In their own words · checked verbatim
I'm told that few computer-related industries have as massive a gap between the open and closed-source versions as EDA does.
So, the AI writing RTL is not the groundbreaking part.
Claiming that the design closes timing relies on an estimate, and so is maybe getting ahead of itself.
This is directional. It smells like the future.
Going agentic means changing from that previously lucrative license revenue model.
There's a reason why they call tapeout 90 days of glory until the chips come back. Nothing sucks more than getting silicon from TSMC and seeing flaws right off the bat.
He feels more comfortable if the design is done by AI and verification done by humans than the other way around.
The problems are going to get ironed out because customers demand this and we're getting a situation where the AI and domain experts are putting their heads together to solve problems. The future is here, old man.
Figures
| NYU's GPT-2 RTL accuracy in 2020 | 94.8% | 6:10 |
| Christina Lee's Phase 1 MAC array clock | 900 MHz to 1 GHz | 10:15 |
| OpenAI Jalapeno RTL-to-tapeout time | 9 months | 12:16 |
| OpenAI chip team size | 20 to 30 people | 13:17 |
| Verification share of chip development time | 50% to 70% | 16:20 |
Glossary
- EDA
- Electronic design automation: the software tools needed to design chips, dominated by a few vendors like Synopsys and Cadence.
- RTL
- Register-transfer level: the hardware description layer (Verilog/VHDL) that describes data flow and logic — the 'code' of a chip.
- PDK
- Process design kit: a confidential set of process parameters maintained jointly by foundries and EDA vendors, tightly protected by NDA.
- PPA
- Power, performance, area: the three key metrics for evaluating chip design quality, suitable for closed-loop optimization.
- tapeout
- The step of handing the fully verified design data to the foundry to manufacture real chips.
How to listen
Semiconductor investors, chip company decision-makers, and engineers focused on AI adoption who want to judge whether 'AI chip design' is a real inflection point or just fundraising talk.
The opening EDA terminology primer (first minute) — those who understand the chip design flow can skip it.