AI Designing Chips Is Real; Verification Is Still the Number One Bottleneck
AI can already write RTL on its own, but the real chokepoint in the entire chip pipeline is verification: it eats more than half of development time, yet AI cannot answer "what should be tested." OpenAI's twenty-person team can shorten the front end, but the back end still has to be left to humans.
The argument · tap a timestamp to hear it
K3 has only a front end, no back end
The original material behind "AI tapes out in 48 hours" is a small inference accelerator called Nano KPU that Kimi announced: 238,000 parameters, about 1.46 million standard cells, 0.277MB SRAM, claimed to close timing at 100 MHz within 4 square millimeters with decode throughput of 8,700 tokens/s. But the host looked closely: this batch of RTL only had functional verification, with no cell placement, routing, physical verification, or sign-off; the so-called "timing closure" relies on estimates, 100 MHz is not impressive in a 45nm open-source library either, since by hand with the same library you can hit 20-450 MHz, and commercial processes can reach 1-3 GHz. K3's goal is not to build a good chip, but to prove an agent can autonomously reach functional completeness.
AI writing RTL is not news at all
Many people think AI writing chips only started with K3, but back in 2020 at NYU someone used GPT-2 to generate beginner-level RTL, with reports claiming 94.8% accuracy; the now-defunct eFabless ran an AI design competition, and a design Will Salcedo generated with GPT-4 actually went to tapeout, one of the earliest LLM-designed tapeouts the host knows of. "AI writes RTL" is not itself the innovation; what actually changed is that an agent can run unattended from start to functional completeness, distilling out process autonomy.
The agent's future is being wrapped around the toolchain
While fully autonomous design is still nowhere in sight, the real product form is wrapping an LLM around the EDA toolchain: the LLM directs deterministic EDA tools through interfaces like MCP and APIs, just as Claude Code lets a model call computer tools. The long-term goal of Synopsys, Cadence, and Siemens is to open up their own stacks and hand data feedback and control to agents that can run for hours or even overnight. Siemens played a demo at Semicon Taiwan: letting an agent drop hundreds of standard cells one by one into a simulator to measure load, speed, and power for later designs to look up. Redoing this tedious work for every process node change is exactly the kind of thing to hand to AI before leaving the office.
Even the best results cannot do without a human in the loop
The post by former xAI engineer Christina Lee is, in the host's eyes, the most convincing breakdown. Her meta-harness has an inner and outer layer: the inner layer lets the model call EDA tools to write RTL, synthesize, place and route, and verify; the outer layer lets the model review what was right and wrong in the previous round, propose improvements, and run again. The first stage only did a MAC multiply-accumulate array, pushing through multiple rounds of iteration to 900 MHz to 1 GHz; the second stage connected the MAC to SRAM and other modules, and complexity immediately rose. Note that the human always holds the steering wheel: the so-called goal strings were likely provided as reference by the outer model, but the filtering and final confirmation power is in human hands. AI is not the boss, it is the co-pilot.
What is truly scary about Jalapeno is the 20-person team
OpenAI's Jalapeno demo had many people fixating on "only 9 months from RTL to tapeout." The host reminds us: Synopsys had previously said on an unrelated occasion that using their tools, without AI, also takes about 9 to 12 months; the chip itself is not complex, and the starting point is unclear too, since the architecture concept only began in October 2024. What really stands out is the team size: only 20 to 30 people stood up when the talk ended. And this group's token consumption has long ranked near the top of OpenAI's internal leaderboard, with RTL still being changed the day before freeze. If such a small team can pull it off, future chip roles will need an order of magnitude fewer people, which may be exactly why they did not emphasize it in the slides.
Verification is the real chokepoint in AI chip design
The whole industry talks up the front-end RTL while glossing over the back end: OpenAI's launch slides dwell a lot on spec and RTL, and the host guesses the back end was probably handled by partner Broadcom, thanked only once on slide 34; Lee also handed the back end to Yosys/OpenLane. The mechanistic asymmetry is this: PPA (power/performance/area) optimization is a closed loop, generating, verifying, and measuring PPA, so AI has a clear reward signal; verification is not, because a test passing or failing cannot tell AI how far it is from full coverage, and "what should be tested" still can only rely on humans. Once a chip bug is taped out it cannot be changed, so seeing a defect the first time you lay eyes on the TSMC silicon is the most crushing thing. This explains why verification can eat 50 to 70% of development time, and echoes Shibo Chen's line that "AI does the design, humans do the verification" is what makes people feel safe.
The front-end wrapper's biggest enemy is OpenAI
A large number of startups have sprung up in Silicon Valley wrapping frontier models with proprietary knowledge to write RTL. The risk the host sees is this: Anthropic and OpenAI themselves both own the models and are building chips, so as soon as they decide to open up the models used for chips, the front-end wrapper's differentiation is gone. So he would rather look at teams moving toward the back end and verification, where end-to-end is where the moat is. How fast is this field moving? Just as he was writing, Architect Labs announced that the Redwood chip was produced and verified entirely by AI, with the spec written only by two architects; even TSMC's 3D IC talk used "agentic AI." The host worries his own judgment will be overturned by new news in a week or two.
In their own words · checked verbatim
I'm told that few computer-related industries have as massive a gap between the open and closed-source versions as EDA does.
So, the AI writing RTL is not the groundbreaking part.
Claiming that the design closes timing relies on an estimate, and so is maybe getting ahead of itself.
This is directional. It smells like the future.
Going agentic means changing from that previously lucrative license revenue model.
There's a reason why they call tapeout 90 days of glory until the chips come back. Nothing sucks more than getting silicon from TSMC and seeing flaws right off the bat.
He feels more comfortable if the design is done by AI and verification done by humans than the other way around.
The problems are going to get ironed out because customers demand this and we're getting a situation where the AI and domain experts are putting their heads together to solve problems. The future is here, old man.
Figures
| Accuracy of NYU's GPT-2-generated RTL in 2020 | 94.8% | 6:10 |
| Christina Lee's first-stage MAC array clock | 900 MHz to 1 GHz | 10:15 |
| OpenAI Jalapeno's time from RTL to tapeout | 9 months | 12:16 |
| OpenAI chip team size | 20 to 30 people | 13:17 |
| Share of chip development taken by verification | 50% to 70% | 16:20 |
Glossary
- EDA / Electronic Design Automation
- The software tools needed to design chips, dominated by a handful of vendors such as Synopsys and Cadence.
- RTL / Register Transfer Level
- The hardware language layer that describes data flow and logic in Verilog/VHDL and the like; it is the chip's "code."
- PDK / Process Design Kit
- A confidential process parameter package maintained jointly by foundries and EDA vendors, tightly protected under NDA.
- PPA / Power, Performance, Area
- The three major metrics for evaluating chip design quality, directly usable for closed-loop optimization.
- tapeout
- Handing layer upon layer of verified design data to the foundry to manufacture a real chip.
How to listen
Semiconductor investors trying to judge whether "AI designs chips" is a real inflection point or fundraising talk, chip company decision-makers, and engineers watching AI adoption.
The EDA terminology primer at the start (minute 1); anyone who understands the chip design flow can skip it.