Bigger photomasks aren't technical; they're TSMC and ASML's economic answer
High NA EUV halves the exposure area and forces painful stitching; TSMC and ASML chose instead to double photomask size, trading a costlier supply chain for full-field exposure.
The argument · tap a timestamp to hear it
Half the field forces stitching two exposures
High NA EUV increases numerical aperture from 0.33 to 0.55, requiring eight times the light cone. This halves the field of view to roughly 16.5×26mm—half the standard full field of 33×26mm. A single AI chip now requires two exposure passes, A and B, stitched together. Ten years ago, mask makers wouldn't invest in larger masks without chipmaker commitment, and chipmakers wouldn't spend capital before adopting low-NA EUV. The industry accepted this field reduction as a trade-off, and now must rectify it.
TSMC's $350M objection masks the real cost problem
TSMC SVP Kevin Tang cited a $350 million per machine cost for high NA EUV, paired with 20 to 40 megawatts of power draw. But the real complaint, the narrator argues, is cost of ownership: half the field cuts throughput so severely that multi-exposure using older methods looks cheaper by comparison. TSMC isn't objecting to the machine price itself, but to the hit on production economics from a shrinking field.
Stitching works in theory, but engineers and designers reject it
IMEC and ASML have both published papers proving stitching is technically sound. But TSMC engineers, the narrator says, show the same reluctance a father sees on his son's face when told to lose weight—they simply don't want to do it. Chip designers resist even more, because stitching carves a ‘Korean DMZ’ through their design, bisecting what should be whole and sacrificing design flexibility. This emotional calculus—not engineering—drives the industry to spend on bigger masks rather than tolerate stitching.
Bigger photomasks are the real fix, not a stitching workaround
A 6×12 inch photomask restores full-field exposure for high NA EUV. By Intel's account, this lifts scanner throughput by 23% to 50% (the narrator guesses toward the higher end), cuts the cost gap with low-NA EUV in half, and hands chip designers full layout freedom. ASML CEO Christophe Fouquet called it a ‘no-brainer’ as early as October 2024, yet the real challenge remains: getting the entire supply chain to move toward an obvious choice.
Even low-NA tools can tap the bigger-mask throughput windfall
Once a 6×12 inch photomask materializes, ASML will install it in existing low-NA EUV tools. Doubling mask area at the same 0.33 numerical aperture means larger AI chip designs can fit in one pass, or the same design can be printed twice simultaneously. Estimates suggest a low-NA EUV tool with a 6×12 inch mask could reach 450 wafers per hour or higher—and paired with a tri-pulse light source, throughput climbs further.
Making one perfect photomask is straightforward; volume production is the barrier
A photomask blank begins with 40 alternating layers of molybdenum-silicon (each pair roughly 7 nanometers thick) sputtered onto a glass substrate, then stacked with insulating, absorbing, and protective layers—all done near-zero defect. The narrator emphasizes: producing one flawless mask, or two, or even a few is not hard. The real challenge is scaling this into high-yield, high-volume manufacturing. That is the bottleneck the mask makers and their entire upstream supply chain must solve.
The photomask ecosystem is nearly all single-source suppliers
From glass blanks to protective pellicles to pattern-writing and defect inspection tools, almost every step in the larger-mask chain depends on one or two vendors. The narrator flags this as the biggest risk: a single supplier's technical misstep or supply disruption ripples through the entire chain, causing concrete delays. With 2031 pilot production five to seven years away, the supply chain is moving—but the single-vendor lock-in at almost every node remains unchanged.
Photomasks weren't cheap before; who pays to double down?
By Micron's 2025-26 economic forecast, an EUV photomask set costs six times more than a conventional optical mask but lasts only one-fifth as long. More masks per set are needed as nodes shrink. Equipping a fab for larger masks means buying new tools that cost 20% to 100% more than legacy 6-inch hardware. The narrator pins the bill on foundries and their customers—Nvidia, AMD, even OpenAI and Anthropic—but acknowledges no one knows whether AI demand will justify the investment in a few years.
In their own words · checked verbatim
My informal evaluation is that it sucks to start.
the looks on the faces of TSMC people when I mention stitching are much like the look that I make when my dad tells me that I should just lose a few kilograms.
ASML has been publicly banging a double-sized mass drum as early as October 2024 when CEO Kristoff Fuket said that it was a no-brainer.
Virtually everything is going to have a single source.
UV massets not only cost six times that of regular optical mass sets, but also last a fifth as long.
Figures
| Low NA EUV numerical aperture | 0.33 | 1:02 |
| High NA EUV numerical aperture | 0.55 | 1:02 |
| High NA EUV machine cost and power draw | $350 million; 20-40 megawatts | 3:05 |
| Throughput gain from 6×12 inch photomasks on high NA EUV | 23-50% | 5:06 |
| Theoretical throughput of 6×12 inch masks on low NA EUV tools | 450 wafers per hour or higher | 6:06 |
| Cost increase for new photomask fabrication equipment | 20-100% more than legacy 6-inch tools | 13:15 |
| EUV photomask set economics vs. conventional optical masks | Six times more expensive; one-fifth the lifespan | 16:16 |
| Timeline for scaled photomask production | Pilot line in 2031; full production by 2033 | 0:02 |
Glossary
- Numerical aperture (NA)
- A dimensionless measure of an optical system's ability to gather and focus light; higher values yield finer resolution.
- High NA EUV
- ASML's next-generation extreme ultraviolet lithography tool with higher resolution and smaller field of view per exposure.
- Stitching
- A technique that joins two or more sequential exposures to form a single complete chip pattern.
- Photomask blank
- An unprocessed glass substrate before circuit patterns are written onto it.
- Pellicle
- A protective film covering a photomask to prevent particle contamination that would cause printing defects.
- LTEM (low thermal expansion material)
- A type of glass used for photomask substrates, engineered to resist deformation at high temperatures.
How to listen
Chip-industry practitioners concerned with advanced-node capacity bottlenecks, semiconductor investors, and engineers wanting to understand EUV photomask economics.
7:09-9:09 photomask coating process details can be skipped without affecting understanding of industry logic.