Unlimited spending can only double advanced-node capacity—not increase it tenfold
Intel's CTO says that even with unlimited capital expenditure, the existing global inventory of chipmaking equipment can only double advanced-process wafer production—while AI compute demand has grown threefold annually over the past decade, and the shortage will only widen.
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The argument · timestamps estimated from transcript position
Waiting for EUV readiness, Intel delayed 10nm by four years
Intel originally planned to mass-produce 10-nanometer chips in 2016 but didn't until 2018—when the announcement broke, the stock fell over 15% while TSMC's rose 13%. Chris Auth, Intel's process chief, explained in hindsight: the team judged EUV wasn't mature, so instead of waiting, they pushed extreme scaling without the new tool, piling innovation burden onto process and engineers. The lesson: each new generation now has a "maturity gate"—technologies that don't meet the bar get deferred to the next node, prioritizing predictable delivery over cramming too much newness into one generation.
— Chris AuthGate-all-around waited 34 years from lab demonstration to production
Gate-all-around transistors—where the gate wraps the channel from all sides—were proven feasible in the lab in 1988, a year before FinFET's 1989 demo. Yet Samsung didn't mass-produce GAA chips until 2022, a gap of 34 years. Chris Auth explained that the industry deployed strained silicon, high-k metal gates, and FinFET as interim technologies that could be deployed sooner, while GAA stayed in the queue. The reason: every transistor architecture shift demands new equipment requirements—a specific deposition gas, a specialized heating chuck—and those inventions take time, often requiring trial and error to validate.
— Chris AuthThe same High-NA EUV tool drew opposite conclusions from Intel and TSMC
Intel adopted High-NA EUV for its 14A process; TSMC publicly stated it's not economical for them at this stage. The difference lies in backside power delivery: Intel moved power lines to the wafer's back side, freeing front-side space so signal lines are less congested, and one High-NA exposure suffices. TSMC has no backside power, so its metal pitch remains tight—it needs multiple EUV exposures to compensate, making High-NA unhelpful. Auth said this reveals that the same tool yields completely different conclusions depending on architecture—the fork in the process roadmap often matters more than the lithography tool itself.
— Chris AuthStacked transistors are bottlenecked by interconnect, not stacking geometry
CFET (complementary field-effect transistor) stacks n-type and p-type transistors vertically, theoretically fitting double the transistor count in the same area—Jack Kavalieros, head of transistor research, calls it the ultimate transistor structure. But the real bottleneck is not stacking; it's the wiring that used to run above or below the transistor now piercing vertically through the space between them. Aspect ratios for etching and filling grow steeper, making both harder, and deposition can leave unfilled voids. Today's lab versions are drastically simplified—just one wire per transistor type—to validate the interconnect scheme; the ultimate form is still far off. Heat dissipation with nowhere to go is another constraint 3D stacking introduces for logic chips.
— Jack KavalierosChiplet bonding pitch has shrunk to 0.45 micrometers
Traditional packaging routes signals through die edges—as dies grow, communication bandwidth doesn't scale as fast as compute, a classic area-to-perimeter problem; for AI chips, inter-chip data speed is often the true workload bottleneck. Hybrid bonding directly fuses copper interconnects between chips, eliminating bulky solder balls. Tyler Osborn, Intel's packaging director, noted that 15 years ago, first-generation interconnect spacing was 130-150 micrometers; today's production Foveros reaches 25 micrometers; papers presented at this year's industry conferences have already validated reliability data for 0.45-micrometer spacing—another full order of magnitude smaller than current production.
— Tyler OsbornUnlimited capital can only double capacity—with existing equipment
CTO Pushkar Ranade was asked: with unlimited capex, how much can current global equipment inventory increase advanced-node wafer output? Not tenfold—roughly twofold. The bottleneck is not just ASML's EUV machines, which ship fewer than 100 per year, divided among Intel, TSMC, and memory fabs; nearly every equipment type faces acute supply shortage. Once a process locks in (say, 18A), it's married to a specific tool and vendor—no swapping for a substitute. Meanwhile, AI compute demand grew threefold yearly over the past decade. The supply and demand curves are widening apart.
— Pushkar RanadeAdvanced foundry consolidated to three players—scale is destiny
Ranade observed that semiconductor foundry economics are manufacturing's purest form of scale economics. After building a fab, roughly 80% of the cost structure is fixed; each additional percentage point of capacity utilization or yield yields not linear, but step-function returns. This explains the industry's 40-year journey from 20-plus foundries to three today: Intel, TSMC, Samsung. On process technology, Intel trails TSMC by only a few percentage points; the real gap is scale—TSMC ships roughly three times Intel's volume. Catching up on scale is a gradual process with no shortcuts.
— Pushkar RanadeLithography cost growth outpaces fab economics—rethink required
Over the past 20-30 years, fab construction costs roughly double every 4 to 5 years, with lithography, the most expensive module, rising even faster: today a High-NA EUV tool with support systems costs about $400 million. If that pace continues, in four years it would reach $800 million—plainly unsustainable. Ranade hinted the industry must fundamentally rethink fab design: Is today's cleanroom complexity standard genuinely necessary? This reasoning drives Intel and Musk's Terafab project—not simply replicating existing capacity, but redesigning the factory logic from scratch.
— Pushkar RanadeIn their own words · checked verbatim
EUV was probably the big thing. When we started to define 10 nanometer, the conclusion was EUV was not ready.
Chris Auth3:22
High-NA’s a good example of where, because of the architecture of our technology versus TSMC’s, we make different conclusions off of the same tool set.
Chris Auth13:13
One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you’ve waited too long.
Kevin Fischer23:33
There is a crossover point where ruthenium will have much better conductivity, better resistivity than copper. That’s roughly in the 20-nanometer pitch range
Jack Kavalieros29:30
Not 10X, but probably 2X, yes.
Pushkar Ranade48:00
There are only three foundries left at the advanced node for that exact reason.
Pushkar Ranade53:14
Today, a High-NA EUV scanner and all its associated equipment costs like $400 million.
Pushkar Ranade1:01:02
Had we known what we know today, we would have invested more like a year ago. Knowing what we know now, I think we’ll be investing more.
Pushkar Ranade1:07:54
Figures
| 10nm planned production year | 2016 (slipped to 2018) | 3:22 |
| Intel stock drop on 10nm delay announcement | over 15% | 3:22 |
| EUV lithography wavelength | 13.5 nanometers | 13:13 |
| High-NA EUV numerical aperture | 0.33 to 0.55; prints features ~1.7x smaller in one exposure | 13:13 |
| Standard EUV lithography tool price | ~$200 million | 13:13 |
| ASML EUV annual output | fewer than 100 units | 48:00 |
| Advanced-node capacity ceiling with existing equipment | 2x maximum, not 10x | 48:00 |
| TSMC annual capex | ~$50 billion | 53:14 |
| Intel annual capex | ~$20 billion | 53:14 |
| High-NA EUV tool total cost | ~$400 million | 1:01:02 |
Glossary
- EUV (Extreme Ultraviolet Lithography)
- Light at 13.5-nanometer wavelength used to print chip circuit patterns.
- High-NA EUV
- New-generation EUV tool with widened lens aperture angle, printing smaller features in a single exposure.
- Gate-all-around transistors
- Transistor structure where the gate completely surrounds the channel from all four sides.
- CFET (complementary field-effect transistor)
- Transistor architecture that vertically stacks n-type and p-type transistors.
- Backside power delivery
- Chip design that moves power lines to the back side of the wafer, freeing front-side space for signal lines.
- Hybrid bonding
- Packaging technology that directly fuses copper interconnects between chips without solder bumps.
How to listen
Investors tracking AI compute supply constraints, engineers and founders making chipmaking or AI infrastructure decisions.
Skip 6:28–39:45 (dense materials science); jump to 48:00 for capacity and competition.